Implementation of Buffer Cache Simulator for Hybrid Main Memory and Flash Memory Storages∗
نویسندگان
چکیده
A buffer cache mechanism is usually employed in modern operating system to enhance the performance that is limited by slow secondary storage. In this paper, we present the implementation of a trace-driven simulator for buffer cache schemes that consider DRAM/PRAM hybrid main memory and flash memory based storages. The goal of simulator is to analyze the legacy buffer cache schemes by measuring the number of write operations on PRAM and the number of erase operations on flash memory.
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